Creonic Unveils CCSDS 131.2 Wideband Modulator IP Core Achieving 1 GSymb/s
Kaiserslautern, Germany, August 3, 2023–Creonic, a leading provider of state-of-the-art IP cores for digital communications, proudly announces the launch of its latest innovation, the CCSDS 131.2 Wideband Modulator IP core.
The design is fully compatible with Creonic's proven CCSDS SCCC Encoder, CCSDS 131.2 Wideband Demodulator, and CCSDS SCCC Turbo Decoder IP cores, creating a comprehensive and efficient ecosystem from a single vendor. The IP core’s design allows it to achieve symbol rates of up to 1 Gsymb/s on state-of-the-art FPGA devices.
The Creonic CCSDS 131.2 Wideband Modulator IP core acts as an advanced inner transmitter, encompassing crucial functionalities such as mapping, Physical Layer (PL) framing, and modulation. Additionally, the core performs baseband interpolation and output gain adjustment, ensuring a sophisticated and optimized baseband signal for subsequent DAC and RF front-end processing.
With AXI4-Stream data interfaces, the IP core seamlessly integrates into any design, ensuring a hassle-free implementation process. Additionally, the memory-mapped AXI4-Lite interface allows for effortless configuration and monitoring of the IP core, empowering users with convenient control over its functionalities.
The IP core boasts a small hardware footprint with no Block RAMs required, making it an optimal choice for resource-constrained applications without compromising on performance.
The IP core is available for ASIC and FPGA technologies such as AMD Xilinx, Intel, and Microchip. It comes as a source code or netlist license with a bit-accurate precompiled software library for running simulations in C/C++/Matlab environments.
For more information go to: www.creonic.com
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